The next generation of Ryzen AI 300 series laptops will be available soon

They will be equipped with a new generation processor highlighting several important entities such as the CPU, the GPU and the NPU.

The next generation of Ryzen AI 300 series mobile processors is just around the corner, and they will be integrating a new generation of silicon that will feature several key units, such as the CPU, GPU, and NPU.

The next generation of Ryzen AI 300 series mobile processors is just around the corner, and they will be integrating a new generation of silicon that will feature several key units, such as the CPU, GPU, and NPU.

A new block diagram has surfaced, showing how AMD has organized everything inside. The Strix Point silicon die measures around 225 mm², which is 66% larger than the previous generation (Phoenix at 135.99 mm²).

A new block diagram has surfaced, showing how AMD has organized everything inside. The Strix Point silicon die measures around 225 mm², which is 66% larger than the previous generation (Phoenix at 135.99 mm²).

Strix Point Block Diagram, CPU

Strix Point Block Diagram, CPU

On the left side of the block diagram is the central processing unit (CPU) section, where you can see the four Zen 5 cores at the top, each featuring 1 MB of L2 cache and sharing a 16 MB L3 cache. Below that are the eight small Zen 5C cores, each with 1 MB of L2 cache and sharing an 8 MB L3 cache.

On the left side of the block diagram is the central processing unit (CPU) section, where you can see the four Zen 5 cores at the top, each featuring 1 MB of L2 cache and sharing a 16 MB L3 cache. Below that are the eight small Zen 5C cores, each with 1 MB of L2 cache and sharing an 8 MB L3 cache.

The various modules within each core are also visible, such as the branch predictor, instruction prefetcher, integer execution, floating-point units, caches, etc.

The various modules within each core are also visible, such as the branch predictor, instruction prefetcher, integer execution, floating-point units, caches, etc.

Over on the right is the graphics processing unit (GPU) section, where we can see eight work group processors (WGPs) of the RDNA 3.5 architecture, each featuring two compute units (CUs) for a total of 16 CUs or 1024 stream processors, along with 512 KB of L1 cache, 2 MB of L2 cache, primitive and raster units, and four render backends (RB+) and a media engine (on the right) that’s complimented by a display engine at the top.

Over on the right is the graphics processing unit (GPU) section, where we can see eight work group processors (WGPs) of the RDNA 3.5 architecture, each featuring two compute units (CUs) for a total of 16 CUs or 1024 stream processors, along with 512 KB of L1 cache, 2 MB of L2 cache, primitive and raster units, and four render backends (RB+) and a media engine (on the right) that’s complimented by a display engine at the top.

Finally, in the upper right corner is the neural processing unit (NPU) section, which includes the AI central module in an 8×4 layout, eight memory modules, and the NPU logical control unit and cache, which take up a significant amount of space.

Finally, in the upper right corner is the neural processing unit (NPU) section, which includes the AI central module in an 8×4 layout, eight memory modules, and the NPU logical control unit and cache, which take up a significant amount of space.

Around the edges of the die are the DDR5-5600/LPDDR5X-7500 memory controllers and PHYs, along with display PHYs, USB 4/3/2, PCIe 4.0 x4, and more.

Around the edges of the die are the DDR5-5600/LPDDR5X-7500 memory controllers and PHYs, along with display PHYs, USB 4/3/2, PCIe 4.0 x4, and more.